Quotation board system



Dec. 10, 1968 E. l. GERTLf-:R ETAL 3,416,134

QUOTATION BOARD SYSTEM mea April 12, 196e 15 sheets-sheet 1 PAR|TY(2) FIG. 5o

ATTORNEYS Dec. l0, 1968 E. GERTLr-:R ETAL 3,416,134

QUOTATION BOARD SYSTEM Filed April l2, 1966 15 Sheets-Sheet 2 f: l: l Il s1 I A il s: E

ATTOR NEYS Dec. 10, 1968 15 Sheets-Sheet 3 Filed April l2, 1966 DeC- 10, 1968 5,1, GERTLER ETAL 3,416,134

QUOTATION BOARD SYSTEM l5 Sheets-Sheet 4 Filed April l2, 1966 Dee 10, 1968 E. GERTLER ETAL 3,416,134

QUOTATION BOARD SYSTEM Filed April l2, 1966 15 Sheets-Sheet 5 (|04 |o5` 5 STAGE SAMPLE A GQUNTER PULSE B -r Tesa GENERATOR RESET TG2 -v--A. LAO L Ao o SHAPER-T T T /me AoRo A. o A.

SHAPERd ||S\ SMC SM2 25 ATA PD-Al l H6 R'ADY RESET ne "97 i 32| c o (Tw 'V-A| |4|7=DR A| 'j SM COUNTER4 0 T T @5B-T G STAGES SM n INPUTSQ'I SMM INVENTOR. 38 EUGENE LGERTLER etal' SM223 BY SM2 SM 52+53 SM24 di.; wird.. 9&4., elan SM25 ATTORNEYS DeC- 10, 1968 E. GERTLER ETAL 3,416,134

QUOTATION BOARD SYSTEM Filed April l2, 1966 15 A, ./57 FIG.

Jcs-Sheet 7 CLOSE HUN MESSAGE 32 KC T BI D LTTN |75 OUTPUT TRCTSPFUQR TRANSFER 6T DELAY OTC-5 E i A, -POTD USEAELE Ao R O *W M Es-AGE OT |75 T OT mom-95| I RESET oTca -C- +(22O 223) |78 FULL |e| |89) RANGE -v-A o A| o K s|GNALs OTCYZO T 88; T

79 Q o a LAST SALE f5 lh i.; slsNALs H j U LsK A86 OTC 27 |87 n OTC (Lu-92) (W) |NvENToR C EUGENE 1:. GERTLER etal (22o- 223) '84 01920 @A 85 02....; yrkgv @.1

oTc (4o-43| ATTORNEYS DeC- 10, 1968 E. |y GERTLER ETAL 3,416,134

QUOTATION BOARD SYSTEM 15 Sheets-Sheet 8 Filed April l2, 1966 m 9m Rg. K OR cN. T l R @55751 N l womoznr wm d, m mmod C mwo mE T N9 l .A \T .oo I 1M zmnlrm C ||l Zmn M ,7M J E m- G P w M LME; C m .M mi 53 4Q Nm. 9W Enh fl. mwod :mi zmn NQ m fl zo.. C

20,. .Hmm :s3 5E r E j Sm m2 Q o HIJZ I :91.3% Q H|12 DeC- 10, 1968 E. l. GERTLER ETAL 3,416,134

QUO'IAT ION BOARD SYSTEM Filed April l2, 1966 15 "Sheets-Sheet 9 A23ww` 2K 190 M2M/WWP#- Azl t-W/I/W-d 2131 A20 MSAKM INPUT A2 8K slc TEST- BUFFER ww AMPLIFIER (LTTNLSTN, :Le-lsv HIGH NULL, OTC 4*92 LOW lNULL) 248 'L CLOSE cTK N2 N2 1 l l) oRlvER -csc -4 246/ DRIVER 250 cTMc: OTC 4|-92 L( INVENTOR.

249 EUGENE 1. GERTLER eval ATTORN EYS Dec. 10, 1968 E. GERTLER ETAL 3,416,134

QUOTATION BOARD SYSTEM Filed April l2, 1966 15 Sheets-Sheet 10 .8 FIG. 21 I2 I INVENTOR. EUGENE I. GERTLER etal ATTORN EYS DCC 10, 1968 E. l. GERTLER ETAL 3,416,134

QUOTATION BOARD SYSTEM 15 Sheets-Sheet 11 Eiled April l2, 1966 Dec.

TNPUT E. l. GERTLER ETAL QUO'IATION BOARD SYSTEM FG. 26A

15 SheetsSheet 12 SOLENOID p AM ICIF'ER NULL DETECTOR MOOR DIGIT/ANALOG ogyJT-MP CONTROL CONVERTER CHSW CLOSE HUN VCHK O c 2'2" HUNDREDS IUNIT N4 (I UNrT) 5 g3: R2 cHMc CLOSE c(T,U,F)sw cL'o'SE ;(T,U,I")I -C QHEO 23 QM" TFERNASCTLgIIq-gs (3 UNITS) (3 UNITS) r. Q'- l (3 UNITS) 20 OTsw OLlEN VOTK 2; A TENS l* OPEN I UNrr) T g3 OPEN (H.L.LT)TSw 265 V-(H.L.LT)TK f :l TENS-HIGH LOW, LAST (3 UNITS) (3 UNITS) (3 UNITS) l H 1 x Ouw OTEN VOUK UNITS I U{ OPEN OPEN (IUNIT) 'EE (H,L,LT)USw P65r (I-I,L,LT)UK I UNITS- HIGH L, i

LOw, LAST (SUNITS) (SUNITS) (3 UNITS) OESw DFN rOI-K FRAOTIONS l F{ OPEN OPEN (I UNIT) `--c| -y (H,L,LT)ESw 65 V(H,L,LT)FK *FRACT HIGH I, LOw, LAST T (3 UNITS) (3 UNITS) (5 UNI s) r-u LS(T,U,F)sw L VLS(T,U,I=)I T TENS, UNITS 3g: U PRAOTIONS (3 UNITS) r (5 UNITS) F (3 UNITS) -U OTc(4I-92)- OTc (4I S2)- DCC. 10, 1968 E. |4 GERTLER ETAL 3,416,134

QUOTATION BOARD SYSTEM l5 Sheets-Sheet 14 Filed April l2, 1966 FIG. 27

T Ao

:NL FF ,282 /ZBI I NHFF FIG. 23

fov 7 2 e j m wyj/ 9N. \l^m E 2 ,@,L .y 5 I M 9 T 4. 2 .T r.. N +6 TN|MU H @L 5 4 T MUM. QJPJU v R u /HW f B M www4 Q m @L n %w Nja J n/J NJN] F 24 WMM L 2 M 2 L Lr Wm Mw wm m W N HH mW M LN W HN CONDITION DIRECTION EQUATloNs l. IMNI- IDN! INVENTOR. EUGENE I. GERTLER e'fol o. IMNI +6,3- IDNI UP b- Il 3. IMNI IDNI ATTORNEYS Dec. 10, 1968 E. GERTLER ETAL 3,416,134

QUOTATION BOARD SYSTEM Filed April l2, 1966 15 Sheets-Sheet 15 FIG. 280

V OUT FIG. 28h

ATTORNEYS United States Patent O 3,416,134 QUOTATION BOARD SYSTEM Eugene I. Gertler and George H. Huber, Cinnaminson,

Walter A. Richman, Woodcrest, and John A. Ciarrocchi and Dennis W. Habgood, Magnolia, NJ., assignors to Ultronic Systems Corp., Pennsauken, NJ., a corporation of Delaware Filed Apr. 12, 1966, Ser. No. 542,057

` 8 Claims. (Cl. 340--154) This invention relates to quotation board systems for the display of prices of stocks, commodities and the like.

Quotation board syste-ms are in use which display one or more price categories of stocks, bonds, commodities, warrants, etc. so that brokers and their customers may be kept informed. For convenience only the term stocks will usually be used hereinafter, and it will be under stood to include these various kinds of property. Some quotation boards provide only current or Last price,

, whereas others provide several price categories such as Close, Open, High, Low, Last, etc.

For greatest usefulness such systems should be capable of rapid updating in a reliable manner, and should be as economical as possible in order to attain widespread use. Further, inasmuch as different brokers may have different primary interests, and such interests may change from time to time, a iiexible system capabale of convenient change of stocks displayed is highly desirable.

The present invention is designed to provide an improved syste'm for accomplishing these objectives.

In the system of the invention, messages are transmitted from a central location via suitable communication lines to the quotation board locations. Each message has a coded stock identification section, a coded price category identification section and a coded price section. Also, a recognizable initial sync pattern and a parity section are advantageously provided to permit eliminating messages which have been transmitted improperly or have become altered in transit.

Commonly the message cover many more stocks and price categories than are likely to be used at any one quotation board installation. Provision is made at each installation to select from the train of messages those stock quotations which can be used at that installation. Provision is also made for enabling a broker to change the stocks displayed on his quotation board in a simple, very convenient manner. This is accomplished by providing manually changeable stock identification characters for each board location, with associated means for simultaneously changing the coding combinations which recognize the lstock message to be displayed at that location.

In sci-called Full Range boards wherein several price categories are displayed for a given stock, all price category sections are enabled upon the recognition of the stock identification in the message for that location. The price category identification in the message enables the category 4section at all stock locations where prices correspond thereto. Thus the selection of the particular stocks is obtained by a joint enabling operation. Then, the displayed price at the selected location or locations is changed if it differs from the message price.

To display the prices, individual digit units are provided at each price location. In the specific embodiment a moveable digit member in the form of an endless belt is driven by a respective motor until the proper digit is displayed, and a detent mechanism insures accurate positioning. To reduce the positioning time, it is desirable to drive the motor in the direction of the shorter path from old to new positions. This is accomplished by developing an analog voltage varying with the displayed digit, converting the desired new digit in the message from digital to analog form, and using special circuits to determine 3,416,134 Patented Dec. 10, 1968 ice the direction of motor rotation and arrival at the desired new position.

To increase the speed of updating, particularly at the beginninig of a day when a rapid sequence of messages would be required to update all categories of a Full Range board, a New High-New Low computer is provided at the board location for determining these prices from a Last Sale message and the then-existing High and Low prices on the board. This markedly reduces the number of messages which must be processed, while still yielding the desired information.

To further reduce the time required for processing messages, those which are not useable at a particular Iboard installation are quickly discarded so that only potentially useable messages are completely processed. Thus the absence of a stock on the board corresponding to a message is used to discard the message. Advantageously this is accomplished by utilizing the non-enabling of the Last price position on the board.

Further features of the invention will be described hereinafter in connection with a specific embodiment thereof.

In the drawings:

FIGS. l and 2 show face views of Full Range and Last Sale quotation boards, respectively;

FIGS. 3 and 4 are perspective views of alpha and numeric sub-modules, respectively, and FIG. 4(a) is a detail of the latter;

FIGS. 5(a) and 5(b) show two message formats;

FIG. 6 is an overall block diagram of the system;

FIGS. 7-25 show circuits for performing the functions indicated in the block diagram of FIG. 6 and may be generally designated as follows:

FIG. 7-Input Register FIGS. 8a, b, c, d Price, Message, SIC Storage Regis ters; Commodity Detectors FIGS. 9, 9a-Resynchronizer and Clock, and waveforms;

FIG. lO-Sync Detector, SM Counter and Control FIG. ll-Parity Check; Good Message Detector; Input Shift Control; Input Transfer Control FIG. l2Message Counter FIG. l3-Message Decoder FIGS. 14, 14a-Output Transfer Counter and decoder FIG. lS-SIC Test and Useable Message Detector FIG. 16e-Output Transfer Control; Clear Board Detector FIG. 17--Message Control FIG. l8-Data Distributor FIGS. 19, l9(a)-Dacon Input circuits FIG. ZO-Dacon sub-module circuit FIG. 21Dacron null detector FIG. 22-Dacron direction detector FIG. 23--Dacron operating equations FIG. 2li- Solenoid and Motor control FIG. ZS-Board Module control FIGS. 26A and 26B show the manner in which assemblies of the units of FIGS. 19-25 are connected to change the prices on the Full Range and Last Scale boards;

FIG. 217 shows the New High-New Low computer; and

FIGS. 28a, b show gate and flip-flop modules widely used in the detailed circuits.

Referring to FIG. l, ra portion of a Full Range board having a desired number of stock locations 31 is shown. At the top of each location are four alpha sub-modules 32 which display the letters of the stock whose prices are given below. Four numeric sub-modules 33 are in the row designated Close at each location, and give hundreds, tens, units and fractions of that price. The rows designated Open, High, Low and Last each contain three numeric submodules for corresponding prices, the hundreds digit being omitted as unnecessary. Green and red lamps G,

R light up when a new high or new low is received. The frications numerals are of distinctive color such as orange, for ready identification. The letters in the stock row m-ay be changed by the stockbroker by inserting a key in holes 34, so that any desired `stock may be selected for display. Changing the letters automatically causes the prices of the newly-selected stock to be displayed the next time the new stock information is received.

FIG. 2 shows a portion of a Last Sale board having locations 35. At each location the Last price of live different stocks are `displayed in corresponding rows. The first four columns 36 display the letters of .the selected stocks. The last three columns 37 display the corresponding Last prices in tens, units and fractions. Hundreds are omitted as unnecessary, since the broker will be aware of the appropriate price.

FIG. 3 shows an alpha sub-module. An endless belt 41 carries letters A to Z and a blank. The leftmost submodule may also have C1, C2, C3 for commodities an-d the other three may have Pr for Preferred. The belt has sprocket holes engaging sprocket drum 42 which is manually rotatable by shaft 40 through bevel gears. The front end of the shaft is slotted to receive a key through a hole in the panel. Drum 42 is geared to an assembly of five Cams 43 which engage respective levers `44 to actuate microswitches 45. Cams 43 are coded to actuate the microswitches in different coding combinations as different letters are brought into view at the front of the submodule.

FIG. 4 shows a numeric sub-module. Digits 0-9 are carried by endless belt 46 driven lby a reversible D.C. motor 47 through a belt drive to sprocket drum 48. The drum is geared to a detent wheel 49 which rotates once for a full traversal of belt 46. Wheel 49 has eleven slots 51 spaced at 1/12 revolution, with a blank 52 for the position twelve. Detent arm 53 is spring-biased into the slots, and withdrawn therefrom by solenoid 54. The arm of the 12-position rotary switch 55 is driven with the detent wheel. The switch contacts are connected to resistors, one `of which is shown at 56, mounted on a printed circuit board 57. These resistors are connected in a ring configuration as explained later for FIG. 20.

In operation, the settings of the microswitches 45 in the alpha sub-modules at a given location recognize the SIC (Stock Identification Code) in a message and enable circuits for the solenoids and motors corresponding thereto. The position of rotary switch S is used to indicate the numeral (MN) then being displayed, and if it differs from the desired numeral (DN) the solenoid and motor are energized to move belt 46 until the desired numeral is displayed. Detent arm 53 and wheel 49 stop movement of belt 46 precisely Vat the desired position, and motor 47 is deenergized. This will be explained in detail later.

FIG. 5A shows one type of message used to supply information to the quotation system of the present invention. The message format is like that described in Patent No. 3,310,782, filed February 27, 1963, by Sinn et al. for Data Message System. In that -application themessages are transmitted from a master station to slave stations distributed around the country to update memories thereat. Here, the messages are used for display purposes.

The message starts with an identifying sync pattern specifically shown as nine l-bits followed by a O-bit. This is followed by a 20-bit SIC section which accommodates four S-bit sections for four alpha characters. The coding of the cams 43 in FIG. 3 agrees with the SIC message coding. A 7-bit message code section MC serves to identify the category of the message (Close, Open, High, etc.), This is followed by a 12-bit Price section sufficient for Ithree BCD (Binary Coded Decimal) digits denoted H, M, L for High, Medium and Low. Throughout the day, when hundreds are not normally transmitted, these correspond to tens, units and fractions. To transmit hundreds, a special code is inserted in the MC section and the coded digit placed in the H position of the Price section. The Volume section is not at present used for this quotation system. The message ends with a 2-bit parity section which gives odd parity for both odd and even bits in the message. In normal updating of a slave station, a given message is repeated after a brief interval, and this is taken into account in the system of the invention.

FIG. 5B shows an alternate message format used for transmission intended specifically for quotation board use. Here the sync section is longer, specifically shown as sixteen 1-bits followed by a 0-bit. The volume section of FIG. 5A is omitted, and the other sections are the same. In practice, the quotation system is designed to use either type of message by suitable switching. To avoid undue complexity, the embodiment described hereinafter is shown for the format of FIG. 5A, and modifications for that of FIG. 5B will be briefiy mentioned.

FIG. 6 is a block diagram of the system intended to give an overall idea of its functioning. Many interconnections and some particular features have been omitted for simplicity, but will be described later in connection with the detailed circuitry. The numbers in the upper right hand corners give the figures where the circuits are shown.

The input message is supplied to a Resync and Clock block 61 which develops QSA, 5B and C signals used extensively to maintain proper synchronization. At present, message bits occur at the rate of l kc. (kilocycles per second), and the q signals occur at that rate but at different phases within a bit interval. The message is supplied to Sync Detector 62, and if the initial sync section is satisfactory, the Parity Check circuit `63 is enabled to check the remainder of the message. Also Shift circuit 64 is enabled to start shifting the SIC and subsequent portions of the message into the Input Register 65. The Sync Detector enables the SM Counter Control 66 which in turn allows SM Counter 6'7 to start counting B pulses at a l kc. rate. This counter controls operations prior to use of the message for updating.

The Input Register has 51 stages to accommodate the bits of the message following Sync, but excluding Parity., At a count -of 52, SHIFT 64 is inhibited so that no more bits enter the Input Register. At a count of 54, the parity check has been completed and, if correct, Good Message Detector 68 is enabled to develop an IT (Input Transfer) signal which transfers the contents of the Input Register to Stock Code, Message Code and Price Data storage registers 71, 72, 73, ready for use. Message Counter 74 insures that the system will operate on only one of two successive duplicate messages.

The output cycle for using the stored information is initiated in 75 by IT, and Output Transfer Counter 76 is released to start counting B pulses. Block 75 also inhibits block 68 from transferring a new message until theexisting message has been processed.

The board is first tested in 77 `at a count of l2 to ascertain whether the stock of the message is on the board, and if the message category is useable. If m0, block 75 is reset, the inhibition on 68 is removed so that a new message can be processed, and counter 76 is reset. If yes, transfer by Output Transfer 78 begins at a count of 15. In the meantime, at a count of 14 if the message is a Last price, a New High or New Low is determined in 79.

Upon storage therein, the SIC from register 71 is supplied to all SIC sections of the quotation board and, if agreement is found in any section (stock on the board), the solenoids and -motors in the corresponding price sections are enabled, as mentioned above. The message code in 72 is decoded in 81 and supplied to Solenoid Control 82 and Motor Control 83 so that control signals will be developed for only the proper price categories. The price data in 73 is rearranged and distributed by 84 to Dacon (Digital to Analog Converter) circuits 85, along with present position signals from the module rotary switches.

The -Dacon circuits determine which, if any, numeric sub-modules need to be changed and provide appropriate signals to Solenoid Control 82 and Motor Control 83. The latter supply signals to the :proper sub-modules on the board to effect the required changes. The solenoid is actuated first, at a count of 15, to withdraw the detent arm, and the motor is actuated at a count of 40. For changes of one or two digits, the motor may not reach full speed before its energization is removed, and may stop short of the proper detent position. Minimum Drive `86 keeps the motor energized to at least a count of 92, thereby giving a 50 millisecond minimum drive signal.

When the numeric changes have been completed, signals from Solenoid Control 82 actuate Clear Board Detector 87 to reset block 75 and terminate the output cycle. Detector y87 is inhibited by block 86 so that it cannot operate until the minimum drive period is over.

The circuit diagrams shown in subsequent figures use digital logic elements. Many types of elements are known in the art and may be used as desired to perform the functions hereinafter described. The specific embodiment here shown uses NOR logic units, examples of which are shown in FIG. 28. These will `be described at this point to facilitate understanding the circuit diagrams.

FIG. 28a shows a NOR circuit of known configuration which need not be described in detail. If any one of the three input lines designated IN is at ground potential, say corresponding to a binary l, the transistor will be cut off and the output line designated OUT will be negative (binary 01). If all inputs are negative, the transistor will conduct and the output will be at groun-d potential. For convenience, negative and ground potentials will usually be referred to hereinafter as low and high," respectively. Thus the circuit functions as an AND gate with polarity inversion for input signals Whose assertion levels are low, and as an OR circuit with inversion for signals whose assertion levels are high. The symbol 305 is used in the drawings. If only one input line is used, and the others left unconnected, the circuit functions as a polarity inverter.

FIG. 28b shows a bistable multivibrator 0r fiip-flop circuit, also of known configuration. The circuit of transistor 306 may be considered the l-side and that of 306 the O-side. When 306 is conducting the "1 output is high (ground) and when 306 is conducting the output is high. The reset input R is arranged so that, when it goes high, it cuts off 306. By the cross-connections, 306 is turned on. Thus in the reset state the 0 output is high and the l output low. In the set state the conditions are reversed. The fiip-op may be switched from one state to the other by a pulse applied to trigger input T, under the control of steering inputs A0 and A1. If A0 is high and A1 low, a positive-going trigger pulse at T will cut off transistor 306', thus turning on 306` and producing the set state wherein the l output is high. With the input voltages to A0 and A1 reversed, the trigger pulse will cut off transistor 306, thus turning on 306' and producing the reset state wherein the 0 output is high. Symbol 307 is commonly used in the drawings, and is referred to as FF.,5

In the detailed drawings a large number of signals are used. Frequently, some signals used in earlier figures are generated in later figures, and this will lbe mentioned. Many signals are shown both unbarred and barred in the drawings, e.g. SHAPER and SHAPER. One is the inverse of the other, and is developed by an inverter, from opposite outputs of a fiip-flop, etc. As used, an unbarred signal usually means that its assertion level is high, and a barred signal that its assertion level is low.

Referring to FIG. 7, an input message having the format of FIG. 5A is fed to a Shaper 88 which reforms the pulses and is then applied as steering inputs to FF89 which eliminates effects of noise. A source of 32 kc. pulses is used in the resynchronizer, as will be described, and the first of these pulses after the steering changes triggers FF89 to the corresponding state. Thus the signals at the 1-output designated SHAPER are those of the input message, but reformed and free of noise. A high level corresponds to a l-bit and a low level to a O-bit. The SHAPER signal is inverted to yield SERIAL INPUT and again inverted to form SERIAL INPUT. These provide steering inputs to the first stage 90 of the input register 65. The register contains 5l stages. If the sync pattern is satisfactory, SHIFT LIMIT (FIG. 1l) at gate 91 will go low and allow A pulses to pass to the trigger inputs of all stages, thereby shifting the message information into the register. When 51 bits have been inserted, SHIFT LIMIT goes high to prevent further shifting. The outputs of the stages are designated IRI to 1R51, and the corresponding barred signals. IRI-20 give the SIC bits, IR21-27 the MC bits, IR28-39 the Price bits, and 1R40- 51 the Volume bits (not used).

FIG. 8a shows the Price Storage Register. IR28-31 represent the most significant digit and are applied individually to four FF stages in box 92. Only the first and last stages are shown in detail. 1R28, 1R28 are steering inputs to stage 92', and IR31, 1R31 to stage 92". IT (FIG. ll) is applied to the trigger inputs of all four stages, and when it occurs the stages assume states determined by the IR inputs. The l-outputs yield QH 23, 22, 21 and 20 respectively, for the four bits of the most significant digit. The O-outputs yield corresponding barred signals. Boxes 93 and 94 are similar to 92 and each has four stages. Box 93 receives IR32-35 and produces QM 23--20 for the middle digit. Box 94 receives IR36-39 and produces QL 23-20 for the least significant digit.

FIG. 8b is similar, but has seven FF stages for the seven bits of the message code. It receives IR21-27 and, upon occurrence of IT, the stages produce MC 26-2 and corresponding barred signals.

FIG. 8c is also similar, but has twenty stages for the SIC bits. The first five reecive IRI-5 and, when triggered by IT, produce SCR1-1 to 1-5, giving the five bits of the first SIC character. Succeeding groups of five are similarly triggered by 1T to produce succeeding SIC characters as indicated. Provision is made to reset the first five stages of this register if an excessive time has elapsed after the last message. DR (FIG. 10) and m RESET (FIG. 14) areapplied through OR 95 to a half-second detector 96. Upon initial application of one of these signals, the SCR RESET output is low and remains low if another signal is applied within a half-second as in normal operation. If not, detector 96 is arranged to cause SCR RESET to go high. This is inverted and applied to gate 97 along with pA to reset the IRI-5 stages. SCR RESET is also applied to Shift Limit FF123 (FIG. 11) to avoid lockup if the FF is in the wrong state when power goes on.

FIG. 8d shows the commodity detectors. For a commodity the first SIC character is C1 or C2, depending on the source of the quotation. C3 is not now used, but provision is made for its future use. IRI-5 (and barred) signals are supplied in proper combinations to decoder gates in 98 to yield C1, C2 or C3 outputs. The codes are shown in parentheses. The outputs go to 0R99 and are inverted to give Cl-|C2-1-C3.

FIG. 9 shows the Resynchronizer and Clock circuits. The outputs of a 32 kc. pulse generator 10-1 is supplied through inverters 102, 103 to a divide-by-32 counter 104. The outputs of the several stages of counter 104 are supplied to Sample Pulse Generator 10S where they are combined to yield different outputs pA, B and fpC. The pulses in each phase occur at a 1 kc. rate. The 0-output of the last stage, TC24, is also taken out. The clock is resynchronized at the leading edge of each l-bit in the message. FF106 is steered toward its set state, and triggered by SHAPER pulses. When set, FF106 steers FF107 toward set, and the next 32K() pulse from inverter 102 sets FF107 and the l-output goes high to reset counter 1104. The set FF107 steers FF108 toward set. The next 32 kc. pulse from inverter 103 sets PP108, the l-output resets PF106, and PF107 is reset by the next pulse to its T input, thereby releasing the reset of counter 104. The counter starts counting from zero, and hence yields outputs properly phased with respect to the data bits.

PIG. 9(a) shows the phases. A occurs at one-half of a SHAPER bit interval, 95B occurs at one-quarter and C at three-quarters, corresponding to counts of 16, 8 and 24 respectively. The input register is shifted by 95A pulses, and hence bits will be inserted therein one-half a bit interval after the corresponding bits in the SHAPER signal, as indicated.

PIG. 10 shows the sync detector and SM counter circuits. A four-stage counter 111 is triggered by pB pulses from gate 112. GM (FIG. 11) is initially low. SHAPER pulses to gate 113 are inverted and applied to the counter reset lines. Consequently bits in the SHAPER signal will reset the counter, but l-bits will not. Accordingly, successive l-bits will allow the counter to count rjbB pulses. When nine have been counted, it is recognized by gate 114 and the gate output goes high to inhibit gate 112 and stop further counting. The high output of 114 also steers PF115 toward set, and it is set by the next 32 kc. pulse. The l-output of PP115 goes high to inhibit gate 113 and prevent counter 111 from bein-g reset. Thus nine or more 1bits (sync of either PIG. 5A or 5B) will lock-up counter 111.

The low 0-output of PF1115 enables gate 116. When SHAPER goes low for the O-bit in the sync pattern, gate 116 is opened and passes a l@ pulse which, by inversion, forms a high Sync pulse which sets Data Ready PP117 This produces high DR and low I outputs. The high DR to gate 114 makes its output low, removing the in hibition on gate 112 and steering FF115 toward reset. The next 32 kc. pulse resets PP115 and the l-output goes low to remove the inhibition on gate 113. Hence the sync detector is ready for another sync pattern when received.

Resetting of P13115 causes its O-output to go high and inhibit gate 116, FP117 is reset by the next C pulse and its O-output goes high to set SM Reset PP118. In its normal reset state, the high `(l-output of FP118 holds SM Counter 119 reset. This reset is removed by setting P12118, and counter 119 starts counting B pulses. The counter stage outputs are decoded (PIG. 11) to form SM54 at a count of 54, and this is applied to gate 121. The next C pulse resets FP118 and its 0output goes high to reset counter 119 and hold it there.

Referring to FIG. 1l, the shift limit circuits will be described first, since this controls entry of the signal into the Input Register. A high DR (or high SCR RESET as previously mentioned) to OR 122 gives a low output which is inverted and sets DC FF123 to produce a low SHIFT LIMIT signal. This enables gate 91 in FIG. 7, as already described, to lshift a message into` the input register. The SM signals to gate 124 decode the counts of 52, 531 and the output is inverted to form S1152-i-53. This is applied to gate 125 along with SM20 to produce a high output at a count of 52 and reset P11123, thereby causing SHIFT LIMIT to go high and inhibit gate 91 to stop further shifting of the Input Register. The count of 52 is at qbB time, ahead of A which produces the shifting, lso that 51 bits will be in the Input Register. The remaining two parity bits will not be entered, but will go the parity check circuits.

Describing the parity check, the TC24 output of the sync counter (FIG. 9) is applied to PP126, connected as a toggle flip-op which changes state at each trigger pulse. The outputs thus enable gates 127, 128 alternately. SERIAL INP UT, applied to both gates, is low for 1-bits and 4high for O'bits. Accordingly, l-bits will allow QSA pulses to trigger PPs 131, 132 alternately as PF126 toggles, so as to count separately the odd and even 1-bits in the message. These PPs have previously been reset by 8 DR through gate 133. For correct (odd) parity, both FFS should end in a set condition, giving low 0outputs. These are applied to gate 134.

As an added safeguard against an incorrect price, the price information in the Input Register is checked for BCD digits from l0 to 15, since only BCD 0 to 9 should be present. IR2-8-30, 32-34, and 36-38 are applied to gates in Detect 135 in proper combinations to recognize BCD 10-15, and the gate outputs combined and applied to gate 134 to inhibit it if one of these numbers is detected. With correct parity and no BCD 10-15', the output of gate 134 will go high, and is inverted and applied to gate 136.

As a further safeguard, the SIC portion of the Input Register is checked to make sure the first character position is not blank. IRI-5 are applied to OR137. If all inputs are low, there is no iirst character and the output of OR137 will be high to inhibit gate 1316. If any input is high, the output of 137 will be low.

Outputs of SM counter 119 are applied to gate 138 to develop SM54 at a count of 54, and this is inverted to form SM54. With the other inputs low, SM5/1 sets GM PF141 to produce a high GM and low m which steer FP142 toward set. RESET at gate 143 is low if the output logic is not busy, and pA lsets FP142 to yield a high IT and low TT. The latter is inverted and resets PP 141. As above described, IT supplies the information in the Input Register to the storage registers of PIG. 8.

FIG. 12 shows the message counter which rejects the second of a pair of duplicate messages occurring before the rst has been processed. Toggle FF145 and P13146 are reset by IT. The resultant high O-output of PF145 inhibits gate 147. When a sync pattern of the next message is detected, to gate 148 goes low and a B pulse sets PP145, yielding a low O-output which enables gate 147. When S1154 occurs at the end of the message, gate 147 passes a A pulse and produces a high MC1 output. This resets GM FF141 in PIG. ll, thereby preventing P13142 from `developing a high IT.

As long as FP141 is set, the high GM signal to gate 112 of PIG. 10 prevents the sync detector from looking for a new sync pattern. The reset of PF141 allows a new sync pattern to be recognized. After rejecting one message, the next DE resets P`F145 and at the same time sets P13146. Resetting FP145 inhibits gate 147 so that MC1 cannot be developed. Setting PP146 produces a thigh 1output which is fed back to inhibit gate 148 so that the next D R is not effective. When IT transfers the message from the input register, it resets FF145 and PP146 to their initial states. If a D R is then present, a new cycle of operation begins. Overall, when a rstme'ssage is accepted, the second is rejected, and the third locked up in the input register until IT is developed.

PIG. 13 shows the message decoding. The MC outp-uts of the storage register of PIG. 8b are supplied to decoder gates in block 151. Table 152 'shows the coding cornybinations for the prices shown at the right. The gates in 151 and the inputs thereto are selected to recognize the various code combinations and yield respective outputs.

FIG. 14 shows the output transfer kcounter circuit. Counter 154 has eight 'stages and counts B pulses. The l-outputs and O-outputs of the stages are brought out as indicated. Prior to the transfer of a message from the input register, PP155 is in its set state, and its high 1-output hold-s counter 154 in its reset condition. Upon transfer of a message, IT resets FF155, thereby releasing the reset to counter 154 and allowing counting to proceed. The various outputs of the counter are applied to gates in block 156 of FIG. 14a in combinations selecte-d to yield the output count signals indicated. These count signals control the timing of the output transfer operations. To stop counter 154, an OT RESET signal from PIG. 16 is applied to PF 155 to set it, thereby resetting counter 154 and holding it reset until a new IT is produced.

FIG. 15 shows the SIC Test and Useable Message Detector. For a message to be useable the corresponding SIC mfust be on either the Full Range or Last Sale boards, or on both. It must also contain a price category which is on the |boards. The test is made at count OTC 12, which is applied as set steering inputs to FF157 and FF158. FF157 is reset by a previous A pulse and its l-output to gate 159 is low. A 32KC pulse sets FF158 and gives a low O-output to gate 159. The output of gate 159 goes high and is inverted to form a low SI-C TEST. This si g nal remains low until the trailing edge of the next qbC pulse triggers FF1S7 to its set state, making its l-output high to inhibit gate 159. The setting of FF157 gives a low (Force nines) used in FIGS. 18 and 27. The next pA pulse resets FF157.

The low S' TEST enables gate 161. If all the category inputs to OR162 are low, a useable category is not present and the high output of 162 is inverted and further enables gate 161. The next C pulse then produces a high u USEABLE MESSAGE signal indicating the message is not useable. If the output of OR162 is low, the message is considered useable insofar as price category is concerned.

The `determination of SIC on the board 'will be described later. If not present on either board, both signals LTI'N and LSTN will be high. These are inverted `and applied to gates 163, 164 along ywith the low 'S' TEST, and the gate outputs will go high .at A to set FF165 and P11166. The respective outputs to gate 167 will be low and the MSG CODE output lwill go high. This will predominate over the low output of O-R162 and produce a high output from gate 161. The setting of FF165, FF166 will also produce high FRK and LSK signals used in the clear board detector of FIG. 16.

If the message SIC is on the board, :one or the other of signals L'ITN, LSTN will be low, leaving the corresponding FF reset .and producing a low MSG CODE signal. This, kwith the low output of OR162, will make the output of gate 161 low, corresponding to a useable message. When l RESET goes low after a message has been transferred t-o the board (described later), it is inverted and resets FF165, FF166.

Referring to FIG. 16, USEABLE MESSAGE is applied to OR171 and the output inverted to yield OT RESET. If the latter is high at OCT 12, corresponding to a nonuseable message, it will reset the OTC counter 154 in FIG. 14 and abort the transfer operation. FF172 will have been reset by a previous OT RESET, yielding a low OT and a high O T, and if the message is useable it will remain reset at OTC 12. Ata count of 15, the lolw TC15 to gate 173 will pass A to set FF172, producing a high OT and low 'O T- which enable the solenoids in the board modules, and also steering -FF 174 toward set. Gate 175, Iwith inputs shown, recognizes a count of 40 and pA sets FCF174 to produce a high OTD and low TD which enable the motors in the board modules. If no clear board condition exists at a count of 220, a compulsory reset is produced. Gate 176 recognizes the count and a QSC pulse resets FF174, and produces a high OT RESET which resets FF172 and the OTC counter of FIG. 14.

The lower portion of FIG. 16 is the clear board detector. K signals from the full range board are applied to gate 178 and those from the last sale board to gate 179. As will be explained, one 01' more of these signals Will be high if the corresponding solenoids in the board modules are energized. When all are de-energized, the solenoids have completed their positioning function and all K signals will be low, giving high outputs from the gates. These .are inverted in OR181 and OR182, combined, and applied as a low input to gate 183. OTD is low whenever a module motor is operating. To insure that the motors are energized sufficiently long to reach the detent positions established by the solenoids, FF18'4 is set at a count of 41 recognized by gate 185 from the inputs shown, making line 186 high to inhibit gate 183. At a count of 92 recognized by gate 187, FF184 is reset, making line 186 low and completing the enabling of gate 183. The resultant high output is inverted and releases the reset to FF188, FF189. The follolwing OTCZU pulse sets FF188 to provide set steering inputs to FF189, and the next pulse sets FF189. The resultant high l-output to OR171 resets FF172, FF174 and OTC counter 154, thereby terminating the output transfer cycle. The delay provided by FF`188, FF1'89 insures that a clear board condition will exist for a short interval before OTC reset, so that a momentary false clear signal will not be elective.

As described for FIG. 15, if the SIC of the message is not on either board, MSG CODE will be high and produce a high USEABLE MESSAGE. In FIG. 16, this will immediately produce a high OT RESET which resets the counter of FIG. 14.

If the SIC is on one board but not on the other, K signals will not be produced for one of gates 178, 179. However, the corresponding FRK or LSK signal will go high. FRK and LSK are applied to OR181 .and OR182, respectively. Assuming the SIC is on the full range board, FRK will be low but the output of gate 178 will go high when the null condition has been reached, making the output of OR181 low. The high LSK to OR1'82 'will make its output low. Thus, when a null has been reached on the full range board, gate 183 will operate as above described.

FIG. 17 shows the manner in which message control signals are developed. A brief explanation of the operating lprocedure lwill facilitate understanding. After a days transactions, say -at midnight, Close signals are transmitted to give tens, units and fractions of the closing prices for the day, and Close Hundreds signals are transmitted separately to give the hundreds digit. The Close signals are also used to set Open, High and Low modules t-o blanks, and the Close Hundreds signals set the Last modules to blanks. This separation of blanking operations avoids excessive power requirements. At the beginning of the next day, Open prices for stocks are transmitted and entered in Open, High, Low and Last positions. Thereafter, during the day, only Last prices for stocks .are transmitted, and' New High (NH) and New Low (NL) prices are determined by a computer at the board location and entered in the corresponding positions. This local computation greatly `decreases the number of messages required to be transmitted. Ocassionally an Open price may be sent out incorrectly, and in such case an Open Correction message is transmitted which is entered in lonly the Open position.

For commodities, opening prices are sent out under a Bid message code, and subsequent prices under a Last message code. Commodities are likely to vary widely in price during the fday and requires .a more elaborate computer. Accordingly, Special High and Special Low messages are transmitted for commodities.

Referring now to FIG. 17, OR circuits 191 are supplied twith the signals indicated, from the message decoder of FIG. 13. Their outputs are supplied to gates 192 which also have 'OTI .applied thereto so that they are effective only when an output is to be supplied to the board modules. The output of gates 192 are inverted to yield the signals indicated. As is apparent, an input CLOSE will produce output m, 'm1-, HTG-H and OW. An input CLOSE HUNDREDS will produce output ISE' HHN-m and HST. An input LAST will produce an output m. It is also inverted, Without gating by OTT, to produce 'Ii-m. An input OPEN will produce output im, L OTW, G-(H .and LS-T. An input OPEN CORR. will produce output Tm. An input BID will produce output "OI- E The input SPEC. HIGH and the computed NH produce m and the input SPEC. LOW and computed NL produce WW". These signals .are also inverted and supplied to 

8. A STOCK QUOTATION BOARD SYSTEM FOR STOCKS, COMMODITIES AND THE LIKE WHICH COMPRISES (A) MEANS FOR RECEIVING QUOTATION MESSAGES INCLUDING A CODED STOCK IDENTIFICATION AND A CODED PRICE SECTION, (B) A QUOTATION BOARD HAVING A PLURALITY OF STOCK SECTIONS FOR DISPLAYING THE STOCK IDENTIFICATION CHARACTERS OF SELECTED STOCKS AND ASSOCIATED PRICE SECTIONS FOR DISPLAYING THE RESPECTIVE PRICES, (C) SAID MESSAGES INCLUDING LAST PRICES AND SAID QUOTATION BOARD INCLUDING HIGH, LOW, AND LAST PRICE SECTIONS, (D) CODING MEANS FOR EACH STOCK SECTION FOR PRODUCING A CODED COMBINATION CORRESPONDING TO THE STOCK DISPLAYED THEREAT, (E) MEANS FOR DETERMINING COINCIDENCE OF THE MESSAGE STOCK IDENTIFICTIONS WITH THE CODED COMBINATIONS OF THE DISPLAYED STOCKS, (F) MEANS RESPONSIVE TO SAID COINCIDENCE FOR DISPLAYING MESSAGE LAST PRICES IN THE BOARD LAST PRICE SECTION OF THE CORRESPONDING STOCK, (G) MEANS RESPONSIVE TO A MESSAGE LAST PRICE AND TO THE THEN-EXISTING HIGH AND LOW PRICES ON THE BOARD FOR DETERMINING WHETHER A LAST PRICE IS A NEW HIGH OR NEW LOW PRICE, (H) AND MEANS RESPONSIVE TO SAID DETERMINING FOR CONTROLLING THE ENTRY OF A SAID LAST PRICE IN SAID HIGH OR LOW BOARD PRICE SECTIONS. 